`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/11/05 17:27:20
// Design Name: 
// Module Name: inst_rom_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module inst_rom_tb;

    logic clka, ena;
    logic [10:0] addra;
    logic [31:0] douta;
    
    inst_rom inst (
        .clka(clka),
        .ena(ena),
        .addra(addra),
        .douta(douta)
    );
    
    always begin
        #10 clka = ~clka;
    end
    
    initial begin
        
        clka = 0; 
        ena = 0; 
        addra = 0;
        
        #100 
        ena = 1; 
        addra = 1;
        
        #50 addra = 3;
        #50 addra = 6;
        #50 addra = 10;
        #50 addra = 12;
        #50 $finish;
        
    end
    
endmodule
